Paper currency validator

ABSTRACT

Longitudinally spaced and laterally spaced sensors are used to sense longitudinally spaced and laterally spaced areas on each inserted bill. The lateral spacing of those sensors enables one of those sensors to engage and sense part of the upper half, and enables the other of those sensors to engage and sense part of the lower half, of each inserted bill - thereby making it possible to prevent the acceptance of a sheet of paper bearing just the upper half of an authentic bill and also making it possible to prevent the acceptance of a sheet of paper bearing just the lower upper half of an authentic bill. The longitudinal spacing of those sensors enables one of those sensors to engage and sense part of the leading half, and enables the other of those sensors to engage and sense part of the trailing half, of each inserted bill - thereby making it possible to prevent the acceptance of a sheet of paper bearing just the leading half of an authentic bill and also making it possible to prevent the acceptance of a sheet of paper bearing just the trailing half of an authentic bill. In addition, the longitudinal spacing of those sensors enables those sensors to provide four signals which correspond to the longitudinally spaced and laterally spaced areas on an authentic bill and which are spaced apart in time; and thus makes it possible to use two sensors to provide four time-spaced signals. The two sensors of the paper currency validator are connected in series; and the series connecting of those sensors and the time-spacing of the signals corresponding to the longitudinally spaced and laterally spaced areas on an authentic bill make it possible for one amplifier to receive and amplify the signals from both of those sensors. The paper currency validator uses phase locked loops as frequency detectors, and thereby provides very compact, relatively inexpensive, and readily adjusted frequency detectors. One of these locked loops responds to signals which are developed as an authentic U.S. 1 dollar bill is engaged and sensed by the sensors, and the other of those phase locked loops responds to signals which are developed as an authentic U.S. 5 dollar bill is engaged and sensed by the sensors; and hence the paper currency validator can test the validity of authentic U.S. 1 dollar and 5 dollar bills. Additionally, the paper currency validator can respond to signals from a dispensing machine with which it is associated to selectively reject such 1 dollar bills, such 5 dollar bills, or all such 1 dollar and 5 dollar bills. The sensors of the paper currency validator engage and sense the border on each inserted authentic bill before they engage and sense the longitudinally spaced and laterally spaced areas on the bill - thereby making it possible to reject any bill which does not have a border. The paper currency validator requires a number of specifically different events to occur within a corresponding number of specifically different time periods; and it utilizes timing circuits which include gates and a binary counter to determine the lengths of those time periods. In using timing circuits which include a binary counter and gates instead of using RC networks, the paper currency validator attains more precise control over the lengths oF the time periods, and it does so at less cost and in a smaller space.

I Carter et al.

[ Mar. 11, 1975 1 1 PAPER CURRENCY VALIDATOR [75] Inventors: Ronald W. Carter; Charles D. Nash,

both of Hot Springs, Ark.

[73] Assignee: UMC Industries, Inc., New York,

[221 Filed: Oct. 11, 1973 211 App]. No.: 405,535

[52] U.S. Cl... 209/1l1.8, 209/DIG. 2, 340/1463 C, 340/1463 Y [51] Int. Cl. B07c 5/344, 606k 9/00 [58] Field of Search.... 209/73, 111.8, 111.7, 111.6, 209/75, 81 M,D1G. 2; 250/219 DQ; 194/4; 340/1463 C, 146.3 Y

[561 References Cited UNITED STATES PATENTS 3,245,534 4/1966 Smith et al 209/11 1.8 3,280,974 10/1966 Riddle ct al. 209/D1G. 2 3,362,532 l/l968 Riddle et al. 209/1 1 1.8 X 3,485,358 12/1967 Hookes 209/75 X 3,509,535 4/1970 340/1463 C 3,706,374 12/1972 Ptacek 209/D1G. 2

Primary E.\'amine"Allen N. Knowles Attorney, Age/11, 0r FirmRogers, Ezell & Eilers [57] ABSTRACT Longitudinally spaced and laterally spaced sensors are used to sense longitudinally spaced and laterally spaced areas on each inserted bill. The lateral spacing of those sensors enables one of those sensors to engage and sense part of the upper half, and enables the other of those sensors to engage and sense part of the lower half, of each inserted bill thereby making it possible to prevent the acceptance of a sheet of paper bearing just the upper half of an authentic bill and also making it possible to prevent the acceptance of a sheet of paper bearing just the lower upper half of an authentic bill. The longitudinal spacing of those sensors enables one of those sensors to engage and sense part of the leading half, and enables the other of those sensors to engage and sense part of the trailing half, of each inserted bill thereby making it possible to prevent the acceptance of a sheet of paper bearing just the leading half of an authentic bill and also making it possible to prevent the acceptance of a sheet of paper bearing just the trailing half of an authentic bill. In addition, the longitudinal spacing of those sensors enables those sensors to provide four signals which correspond to the longitudinally spaced and laterally spaced areas on an authentic bill and which are spaced apart in time; and thus makes it possible to use two sensors to provide four time-spaced signals. The two sensors of the paper currency validator are connected in series; and the series connecting of those sensors and the time-spacing of the signals corresponding to the longitudinally spaced and laterally spaced areas on an authentic bill make it possible for one amplifier to receive and amplify the signals from both of those sensors. The paper currency validator uses phase locked loops as frequency detectors, and thereby provides very compact, relatively inexpensive, and readily adjusted frequency detectors. One of these locked loops responds to signals which are developed as an authentic U.S. 1 dollar bill is engaged and sensed by the sensors, and the other of those phase locked loops responds to signals which are developed as an authentic U.S. 5 dollar bill is engaged and sensed by the sensors; and hence the paper currency validator can test the validity of authentic U.S. 1 dollar and 5 dollar bills. Additionally, the paper currency validator can respond to signals from a dispensing machine with which it is associated to selectively reject such 1 dollar bills, such 5 dollar bills, or all such 1 dollar and 5 dollar bills. The sensors of the paper currency validator engage and sense the border on each inserted authentic bill before they engage and sense the longitudinally spaced and laterally spaced areas on the bill thereby making it possible to reject any bill which does not have a border. The paper currency validator requires a number of specifically different events to occur within a corresponding number of specifically different time periods; and it utilizes timing circuits which include gates and a binary counter to determine the lengths of those time periods. ln using timing circuits which include a binary counter and gates instead of using RC networks, the paper currency validator attains more precise control over the lengths of the time periods, and it does so at less cost and in a smaller space.

FATENTEWRI 1 I975v sumsmfg mQEmmS LE5:

PATENTED MRI 1 I975 sumsp g m mum Mk6 $53 A a? @QDQ mxw Zi s? F T $m PAPER CURRENCY VALIDATOR FIELD OF THE INVENTION The present invention relates to paper currency validators which are able to distinguish between authentic bills and spurious bills.

DESCRIPTION OF THE PRIOR ART SUMMARY OF THE INVENTION The present invention provides a paper currency validator which receives inserted bills and moves them past two sensors that are spaced apart both longitudinally and laterally of the path of those inserted bills. The lateral spacing of those sensors enables one of those sensors to engage and sense part of the upper half, and enables the other of those sensors to engage and sense part of the lower half, of each inserted bill. Consequently, that lateral spacing makes it possible for the paper currency validator to prevent the acceptance of a sheet of paper bearing just the upper half of an authentic bill, and also makes it possible to prevent the acceptance of a sheet of paper bearing just the lower half of an authentic bill. The longitudinal spacing of the sensors enables one of those sensors to engage and sense part of the leading half, and enables the other of those sensors to engage and sense part of the trailing half, of each inserted bill. Consequently, that longitudinal spacing makes it possible for the paper currency validator to prevent the acceptance of a sheet of paper bearing just the leading half of an authentic bill, and also makes it possible to prevent the acceptance of a sheet of paper bearing just the trailing half of an authentic bill. Furthermore, that longitudinal spacing enables the sensors to provide four signals which are spaced apart in time and which correspond to four longitudinally spaced and laterally spaced areas on an authentic bill. In this way, the paper currency validator is able to use two sensors to provide four time-spaced signals from four longitudinally spaced and laterally spaced areas on an authentic bill. It is, therefore, an object of the present invention to provide a paper currency validator which utilizes two longitudinally spaced and laterally spaced sensors to provide four timespaced signals that correspond to four longitudinally spaced and laterally spaced areas on an inserted bill.

The two sensors of the paper currency validator provided by the present invention are connected in series. The series connecting of those sensors, and the timespacing of the signals which correspond to the four longitudinally spaced and laterally spaced areas on an authentic bill, make it possible for one amplifier to receive and amplify the signals from both of those sensors. The use of a single amplifier is desirable because it avoids the cost of two amplifiers, and also because it avoids problems which could arise from the different responses which two individually different amplifiers could make to signals from the two sensors. It is, therefore, an object of the present invention to connect two sensors of a paper currency validator in series relation and to cause those sensors to apply time-spaced signals to the same amplifier.

The paper currency validator of the present invention uses phase locked loops as frequency detectors despite the fact that the oscillators of phased locked loops can, and do, change the frequencies of the signals generated thereby during normal operation of those phase locked loops, and despite the fact that the signals generated by the oscillators of phase locked loops can randomly be in phase with or displaced in phase from the signals applied to those phase locked loops. Specifically, phase locked loops have oscillators which establish center frequencies for those phase locked loops; and whenever the frequency of a signal, that is applied to the input of a phase locked loop, differs slightly from the center frequency of that phase locked loop, the oscillator of that phase locked loop will change the frequency thereof to track the frequency of that applied signal. This means that instead of having a fixed frequency, as do the frequency-sensing circuits of the said Fishel et al application, a phased locked loop has a frequency which can, and does, change during the normal operation of that phase locked loop. Also, the signal generated by the oscillator of a phase locked loop can be in phase with or displaced in phase from the signal applied to the input of that phase locked loop; and where the signal generated by the oscillator of a phase locked loop is displaced in phase from the signal applied to the input of that phase locked loop, that phase locked loop could sometimes require so much time to track and lock up with that input signal that it might fail to respond to that input signal. Also, where the signal generated by the oscillator of a phase locked loop is displaced in phase from the signal applied to the input of that phase locked loop, that phase locked loop can occasionally develop two output signals rather than just the desired output signal. As a result, the use of a phase locked loop as a frequency detector for a paper currency validator does not, without more, seem desirable. However, by equipping a phase locked loop with resistors and capacitors which narrowly limit the extent to which the frequency of the oscillator of that phase locked loop can change, and by providing circuitry which receives the signals from that phase locked loop and which will not respond to a series of fewer than three or more than five signals from that phase locked loop, the present invention makes it possible to use a phase locked loop as a frequency detector for a paper currency validator. It is, therefore, an object of the present invention to provide a paper currency validator with phase locked loops which have resistive and capacitive components that narrowly limit the extents to which the frequencies of the oscillators of those phase locked loops can shift, and also to apply the output signals of those phase locked loops to circuitry which can not respond to a series of fewer than three or more than five signals from either of those phase locked loops.

One of the phase locked loops responds to signals which are developed as an authentic U.S. 1 dollar bill is engaged and sensed by the sensors, and the other of those phase locked loops responds to signals which are developed as an authentic U.S. 5 dollar bill is engaged and sensed by those sensors. As a result, the paper cur' rency validator provided by the present invention can 3 determine the validity of U.S. authentic 1 dollar bills and U.S. authentic dollar bills. That paper currency validator can respond to signals from a dispensing machine with which it is associated to selectively reject such 1 dollar bills, to reject such 5 dollar bills, or to reject all such'l dollar and 5 dollar bills. As a result, if the dispensing machine is able to dispense change for a 1 dollar bill but not for a 5 dollar bill, the paper currency validator will respond to an appropriate signal from that dispensing machine to prevent the acceptance of further 5 dollar bills while continuingto accept 1 dollar bills. On the other hand, if the dispensing machine is able to dispense change for a 5 dollar bill but not for a 1 dollar bill, the paper currency validator will respond to an appropriate signal from that dispensing machine to prevent the acceptance of further 1 dollar bills while continuing to accept 5 dollar bills. If the dispensing machine is incapable of dispensing change for a 1 dollar bill as well as for a 5 dollar bill, the paper currency validator will respond to an appropriate signal from that dispensing machine to reject further 1 dollar bills as well as further 5 dollar bills. It is, therefore, an object of the present invention to provide a paper currency validator which can determine the validity of 1 dollar bills and 5 dollar bills and which can respond to signals from a dispensing machine with which it is associated to selectively reject further l,dollar bills, to reject further 5 dollar bills, or to reject further 1 and 5 dollar bills.

The sensors of the paper currency validator provided by the present invention engage and sense the border on each inserted bill before they engage and sense the four longitudinally spaced and laterally spaced areas on that bill. The engaging and sensing of the border before the engaging and sensing of the laterally spaced and longitudinally spaced areas on the bill makes it possible for the paper currency validator to reject any bill which does not have a border. It is, therefore, an object of the present, invention to provide a paper currency validator which checks the border on each inserted bill.

The paper currency validator requires a number of specifically different events to occur within a corresponding number of specifically different time periods; and it utilizes timing circuits which include gates and a binary counter to determine the lengths of those time periods. In using timing circuits which include a binary counter and gates instead of using R.C. networks, the paper currency validator attains more precise control over the lengths of those time periods; because R.C. networks necessarily include components which can tend to drift. Even resistive and capacitive components which have low temperature coefficients experience some changes as the temperatures thereof change; and hence even R.C. networks which utilize components with low temperature coefficients can not provide the precise timing which is provided by the binary counter and the gates of the present invention. Moreover, the binary counter and gates of the present invention are less costly and occupy less space than do the components of high quality R.C. networks. It is, therefore, an object of the present invention to provide a paper currency validator with timing circuits which utilize a binary counter and gates to provide a number of individually different time periods.

BRIEF DESCRIPTION OF THE DRAWING In the drawing,

FIG. 1 is a vertical section through one preferred embodiment of bill transport that is made in accordance with the principles and teachings of the present invention,

FIG. 2 is a diagrammatic view of a bill in position adjacent the magnetic heads of the bill transport of FIG. 1,

FIG. 3A diagrammatically shows part of the circuit of the paper currency validator of which the bill transport of FIG. 1 is a part,

FIG. 3B diagrammatically shows another part of that circuit,

FIG. 3C diagrammatically shows a further part of that circuit,

FIG. 4 is a detailed showing of the components in the BORDER sub-block of FIG. 3B,

FIG. 5 is a detailed showing of the components in the SPEED ADJUSTING sub-block of FIG. 3A,

FIG. 6 is a detailed showing of the components in the SPEED MAINTAINING sub-block of FIG. 3A,

FIG. 7 is a detailed showing of the components in the OVERLEVEL SENSING sub-block of FIG. 3A,

FIG. 8 is a detailed showing of the components in the MOTOR AND RELAY sub-block and in the CUR- RENT SENSING sub-block of FIG. 3A,

FIG. 9 is a detailed showing of the components in the upper of the FREQUENCY DETECTOR sub-blocks of FIG. 3C,

FIG. 10 is a timing chart, and

FIG. 11 shows an alternate threshold device for the BORDER sub-block of FIG. 3B.

DESCRIPTION OF BILL TRANSPORT Referring to FIG. 1, the numeral 30 generally denotes one preferred embodiment of bill transport that is made in accordance with the principles and teachings of the present invention. The numeral 32 denotes a platform which extends outwardly from the front of the bill transport 30; and that platform will receive the leading edge of each bill which is to be tested by the paper currency validator of which that bill transport is a part. A flange 34 and a counterpart flange, not shown, of generally triangular configurations extend upwardly from the sides of the platform 32; and that platform has an upwardly inclined inner end 38 which merges into a platen 40. An elongated flange 42 and a counterpart flange, not shown, extend downwardly from the elongated sides of the platen 40. The numeral 45 denotes the trailing edge of the platen 40; and that trailing edge inclines downwardly and then terminates in a vertically directed lip, as shown by FIG. 1.

The numeral 62 denotes a headed pin which is secured to the flange 42 and which is adjacent the front of the bill transport 30. The numeral 65 denotes a short pivot which is secured to the flange 42 and which is spaced an appreciable distance to the right of the headed pin 62. The numeral 66 denotes a further headed pin which is supported by the flange 42 and which is spaced to the right of the pivot 65.

The numeral 70 denotes a leaf-type spring which is bent so the right-hand end thereof, not shown, inclines upwardly to bear against the under surface of the platen 40. That spring is bent to have a downwardly opening saddle, not shown, which rests upon the pivot 65, to have an elongated portion which inclines upwardly and to the left from that saddle, and to have a bifurcated left-hand end with fingers that define an upwardly opening saddle. The numerals 72 and 74 denote springs which can be identical to the spring 70; but the bifurcated ends of those springsextend to the right rather than to the left in FIG. 1. The downwardly opening saddle of spring 72 rests upon the headed pin 62; and hence that spring is adjacent the front of the platen 40. The downwardly opening saddle of the spring 74 rests upon the headed pin 66; and hence that spring is adjacent the trailing edge of that platen.

A short pivot 80 is supported by the upwardly opening saddle which is defined by the fingers at the bifurcated end of the spring 72; and that pivot rotatably supports a roller 82. A similar pivot 84 is supported by the upwardly opening saddle which is defined by the fingers at the bifurcated end of the spring 70; and that pivot rotatably supports a roller 86. A further similar pivot 88 is supported by the upwardly opening saddle which is defined by the fingers at the bifurcated end of the spring 74; and that pivot rotatably supports a roller 90.

The numeral 98 denotes an arm which has a hub that encircles the pivot 65. A pivot 100 is fixedly secured to the outer end of the arm 98; and that pivot rotatably supports a roller 102. A short pivot, not shown, which is the counterpart of pivot 65 is secured to the counterpart of flange 42 at a point to the left of pivot 65; and an arm, not shown, which is the counterpart of the arm 98 has the hub thereof encircling that short pivot. A pivot 112 is fixedly secured to the outer end of that arm; and that pivot rotatably supports a roller 114. Springs, not shown, encircle the short pivot 65 and its counterpart pivot; and those springs urge the rollers 102 and 114 upwardly relative to the platen 40.

The numeral 118 denotes an upper platen which normally is disposed in parallel relation with, and in close proximity to, the platen 40. The platen 118 has a downwardly directed flange 120 and a counterpart flange, not shown, at its elongated sides; and each of those flanges has a downwardly opening slot 122 adjacent the front end thereof. The numeral 124 denotes a semicylindrical leading edge of the platen 118; and that semi-cylindrical leading edge is disposed forwardly of the upwardly inclined rear portion 38 of the platform 32. The platen 118 has an upwardly inclined trailing edge 126, as shown by FIG. 1.

The numeral 140 denotes a cover for the bill transport 30; and that cover has a downwardly directed flange 142 and a counterpart flange, not shown, at the elongated sides thereof. The numeral 144 denotes a switch bracket which is secured to the cover 140; and that switch bracket holds a normally open, single-pole, single-throw switch 146 adjacent the front of the platen 118. The numeral 148 denotes a sturdy but thin actuator for the switch 146; and that actuator has a leading edge 150 and a trailing edge 152 which extend downwardly through slots, not shown, in the platens 118 and 40. The leading edge 150 is essentially straight, but the trailing edge 152 is convex. The configurations and inclinations of the leading and trailing edges 150 and 152, respectively, of actuator 148 enable the leading edge and trailing edge, respectively, of a bill to easily raise that actuator upwardly out of the slot in the platen 40. As a result, the switch actuator 148 permits relatively free movement of bills inwardly and outwardly of the bill transport 30.

The numeral 154 denotes a second switch bracket which is secured to the cover 140; and that switch bracket supports a normally open, single-pole. singlethrow switch 156. The numeral 158 denotes a sturdy but thin actuator for the switch 156; and that actuator has a convex leading edge 159 and a straight trailing edge 161 which extend downwardly through slots, not shown, in the platens 118 and 40. The configurations and inclinations 0f the leading and trailing edges 159 and 161, respectively, of the switch actuator 158 enable the leading edge and trailing edge, respectively, of a bill to easily raise that actuator upwardly out of the appropriate slot in the platen 40. As a result, the switch actuator 158 permits relatively free movement of bills inwardly and outwardly of the bill transport 30.

The numeral denotes a third switch bracket which is secured to the cover 140; and that switch bracket is adjacent the rear of that cover. That switch bracket supports a normally open, single-pole, singlethrow switch 162; and that switch has an actuator 164 with a leading edge 166 and a trailing edge 168 which extend downwardly through slots, not shown, in the platens 118 and 40. The leading edge 166 is essentially straight; but the trailing edge 168 is generally convex and is quite short. That trailing edge normally is disposed an appreciable distance below the lower face of the platen 40. As a result, the trailing edge of a bill will not normally engage the edge 168 of the actuator 164 once that trailing edge has moved inwardly beyond that edge. If a person were to attempt to pull a bill outwardly of the bill transport 30, after the trailing edge of that bill had been moved inwardly beyond the edge 168 of actuator 164, the trailing edge of that bill would be intercepted by the inner surface of the leading edge 166 of that actuator. In that event, the actuator 164 would make it impossible for that person to recover that bill in intact form.

The numerals 188 and 190 denote pulleys which are mounted on short pivots, not shown, that are supported by the flange 42; and the numeral 194 denotes a pulley which is mounted on an elongated shaft 182 that is rotatably supported by bushings which are mounted in the flange 142 and in its counterpart flange. The pulleys 188, 190 and 194 accommodate an elongated endless belt 198; and the lower run of that belt is engaged by the upper portions of the rollers 82, 86 and 90. A worm wheel 200 is fixedly secured to the shaft 182; and a worm gear 202 meshes with that worm wheel. That worm gear is mounted on the output shaft 203 of a DC motor 562 which is indicated diagrammatically in FIG. 8 and which is enclosed by a motor housing 204 shown in FIG. 1. That motor housing extends upwardly from the cover 140; and it has its axis perpendicular to the central portion of that cover. The motor 562 is a reversible permanent magnet DC. motor which drives an A.C. generator 560 by means of a connection 564. That A.C. generator is located within the motor housing 204; and that connection is a direct mechanical connection. In the said preferred embodiment of bill transport, the motor 562, the A.C. generator 560 and the connection 564 are parts of a type CYQM Motor With Integral Tachometer Generator which is marketed by the Barber Colman Company as model No. CYQM 23360-3. When the motor 562 is energized in the forward direction, it will directly drive the A.C. generator 560 in that direction, and it will drive the lower runs" of the belt 198 and of its counterpart belt inwardly of the bill transport 30. When that motor is energized in the reverse directioh, it will directly drive the A.C. generator 560 in that direction, and it will drive the lower runs of belt 198 and of its counterpart belt outwardly of that bill transport.

The numeral 206 denotes a mounting bracket which fixedly holds magnetic heads 208 and 210 in spacedapart relation. Those magnetic heads are spaced both laterally and longitudinally of the elongated axis of the bill transport 30. As indicated particularly by FIG. 2, which looks downwardly past those magnetic heads at an outline that generally represents the black-ink face of an authentic US. 1 dollar bill 212, the air gaps of those magnetic heads will sense two laterally spaced, longitudinally extending paths.

The numeral 220 denotes an elongated pivot which has the opposite ends thereof secured to the rear portions of the flange 120 and of its counterpart flange, not shown, on the upper platen 118; and that pivot extends through aligned openings in the flange 42 and in the counterpart flange, not shown, on the lower platen 40. As a result, the pivot 220 enables the upper platen 118 and the cover 140 plus the various components which are mounted on that upper platen and on that cover to be rotated upwardly and away from the lower platen 40. Such rotation is desirable; because it permits ready and free access to the space between the lower platen 40 and the upper platen 118. However, the upper platen 118 will normally respond to its weight, to the weight of the cover 140, and to the weight of the components mounted on that upper platen and on that cover to urge the lower face of the lower run of the belt 198 into intimate engagement with the upper faces of the rollers 82, 86 and 90. The springs 70, 72 and 74 will yield slightly in response to the combined weights of the upper platen 118, of the cover 140, and of the components which are carried by that upper platen and by that cover; but those springs will hold the upper surfaces of the rollers 82, 86 and 90 above the upper surface of the lower platen 40. Those rollers and the rollers 102 and 114 are in register with openings, not shown, in that lower platen.

The bill transport 30 is essentially identical to the identically numbered bill transport in the said Fishel et al application, except that the magnetic head 210 has been shifted closer to the leading edge of the platen 118, and the arm 98 and its counterpart have been mounted on the short pivot 65 and its counterpart pivot instead of being mounted on the same elongated pivot. In the said preferred embodiment of bill transport, the air gaps of the magnetic heads 208 and 210 define parallel lines which are transverse of the longitudinal axis of the platen 118 and which are spaced apart one-half of an inch. The inner faces of the magnetic heads 208 and 210 are spaced apart one-sixteenth of an inch transversely of the longitudinal axis of the platen 118. Consequently, when the vertical centerline of the upper part of the engraved portrait of George washington on an authentic US. 1 dollar bill is in engagement with the air gap of the magnetic head 208, the lower left-hand quadrant of the background for that portrait will be in engagement with the air gap of the magnetic head 210, as indicated by FIG. 2.

DESCRIPTION OF THE CIRCUIT FIGS. 3A-3C, which diagrammatically show the circuit of the preferred embodiment of paper currency validator provided by the present invention, include a number of blocks and sub-blocks. The numeral 230 in FIG. 3A denotes a START AND RUN LOGIC block which contains a three-input NAND gate 232,. Conductors 766, 776 and 780 extend from a SWITCI-I LOGIC block in FIG. 38 to the three inputs of the NAND gate 232. A branched conductor 234 is connected to the output of NAND gate 232; and one branch of that conductor extends to the input of an inverter 238 within a VEND ENABLE LOGIC block 236. The output of that inverter is connected to the upper input of a two-input NAND gate 240 and to a conductor 241.

In the drawing and accompanying description the switches 146, 156 and 162 are switcheswhich have movable and stationary contacts and which have actuators which respond to the leading and trailing edges of bills to move those movable contacts. However, if desired, photoelectric cells and other bill-sensing devices could be substituted for the switches 146, 156 and 162. Consequently, it will be recognized that the term switch as used herein includes photo cells and other bill-sensing devices.

A conductor 850 extends from a VALIDATING AND VENDING LOGIC block 784 in FIG. 3C to the lower input of NAND gate 240. The other branch of conductor 234 extends to the lower input of a twoinput NAND gate 328 within a MOTOR REVERSE LOGIC block 286. The conductor 241 extends to the cathode of a diode 245; and the anode of that diode is connected to a source of regulated plus twelve volts DC. by a resistor 247, to ground by a capacitor 249, and to the upper input of a NAND gate. A conductor 253 connects the output of that NAND gate to a SPEED" MAINTAINING sub-block 358 within a MOTOR CONTROLLING block 354.

A branched conductor 242 is connected to the output of NAND gate 240; and one branch of that conductor extends to the upper input of aa two-input NAND gate 246 within a TIMER block 244. A branch of conductor 766 extends to the lower input of NAND gate 246. The output of NAND gate 246 is connected to the lower input ofa two-input NAND gate 248; and a resistor 250 extends between the source of regulated plus twelve volts DC. and the upper input of that NAND gate. The output of NAND gate 248 is connected to the reset input of a BINARY COUNTER 254; and the output of a PULSE GENERATOR 252 is connected to thecount input of that BINARY COUNTER. The input of the PULSE GENERATOR 252 is connected to a source of sixty Hertz signals. Although different pulse generators could be used, a Schmitt trigger has been found to be quite useful as the PULSE GENERATOR 252; and it acts to steepen the leading edges and to flatten the tops of sine waves that are supplied to it by the source of sixty I-Iertz signals. Although different binary counters could be used, the RCA 4024 seven-stage binary counter has been found to be quite useful as the BINARY COUNTER 254. A conductor 256 extends from the binary four output terminal of the BINARY COUNTER 254 to the upper input of a three-input NAND gate 272 in a TIMER LOGIC block 262. A branched conductor 258 extends from the binary eight output terminal of the BINARY COUNTER 254 to the lower input of a two-input NAND gate 266, to the upper input of a three-input NAND gate 268, and to the middle input of the three-input NAND gate 272. A branched conductor 260 extends from the binary 32 output terminal of the BINARY COUNTER 254 to the middle input of NAND gate 268, to the upper input of a two-input NAND gate 270, and to the lower input of NAND gate 272. A branch of conductor 780 is connected to the lower input of NAND gate 270. A conductor 852 extends from the VALIDATING AND VENDING LOGIC block 784 in FIG. 3C to the lower input of NAND gate 268.

Another branch of conductor 242 extends to the input of an inverter 264 in the TIMER LOGIC block 262; and the output of that inverter is connected to the upper input of the NAND gate 266. A further branch of the conductor 242 extends to the lower input of NAND gate 251; and a still further branch of that conductor extends to the input of an inverter 762 in the SWITCH LOGIC block 738 in FIG. 3B. The remaining. branch of conductor 242 extends to the lower inputs of NOR gates 838 and 840 in the VALIDATING AND VENDING LOGIC block 784 in FIG. 3C.

A conductor 278 extends from the output of NAND gate 266 to the second-uppermost inputs of four-input NAND gates 728 and 730 in an INHIBIT LOGIC block 718 in FIG. 3B. A conductor 280 extends from the out put of NAND gate 268 to the upper input of a fourinput NAND gate 326 in the MOTOR REVERSE LOGIC block 286. A conductor 282 extends from the output of NAND gate 270 to the second uppermost input of NAND gate 326. An inverter 274 has the input thereof connected to the output of NAND gate 272, and it has the output thereof connected to the anode of a diode 276. A conductor 284 connects the cathode of diode 276 to the upper input of a three-input NOR gate 295 in the MOTOR REVERSE LOGIC block 286.

The numerals 288, 290, 292 and 294 denote further three-input NOR gates within the MOTOR RE- VEERVE LOGIC block 286; and branches of conductor 776 extend to the upper inputs of NOR gates 288 and 292. Branches of conductor 780 extend to the middle input of NOR gate 290 and to the lower input of NOR gate 292. A branch of conductor 766 extends to the middle input of NOR gate 294. A conductor 764 extends from the SWITCH LOGIC block 738 to the upper inputs of NOR gates 290 and 294. A conductor 778 extends from that SWITCH LOGIC block to the middle input of NOR gate 292 and to the lower input of an OVERLEVEL SENSING sub-block 296. A branch of conductor 852 is connected to the lower input of NOR gate 288; and a conductor 768 extends from SWITCH LOGIC block 738 to the middle input of that NOR gate and to the lower input of NOR gate 294. A conductor 79I extends from the VALIDATING AND VENDING LOGIC block 784 to the upper input of the OVERLEVEL SENSING sub-block 296. A diode 298 has the anode thereof connected to the output of NAND gate 288, and has the cathode thereof connected to the upper input terminal of NOR gate 295 by the conductor 284. Similarly, a diode 300 has the anode thereof connected to the output of NAND gate 290, and has the cathode thereof connected to the upper input of NOR gate 295 by the conductor 284. A conductor 297 and the conductor 284 connect the output of the OVERLEVEL SENSING sub-block 296 to the upper input of NORgate 295. The output of NOR gate 292 is directly connected to the middle input of NOR gate 295; and the output of NOR gate 294 is directly connected to the lower input of that NOR gate.

The numeral 302 denotes an NPN transistor in the MOTOR REVERSE LOGIC block 286; and a resistor 312 connects the connector of that transistor to the source of regulated plus twelve volts DC. The emitter of that transistor is grounded; and the base of that transistor is connected to the junction of resistors 306 and 308 which coact with a thirteen volt Zener diode 304 to constitute a voltage divider between ground and a source of non-regulated plus 24 volts DC. A capacitor 329 is connected between ground and the collector of transistor 302; and a resistor 310 is connected between ground and the conductor 284, and thus is connected between ground and the upper input of NOR gate 295.

An inverter 314 has the input thereof connected to the collector of transistor 302, and has the output thereof connected to the cathode of a diode 318; and a conductor 316 extends from that cathode to the uppermost inputs of the NAND gates 728 and 730 in the INHIBIT LOGIC block 718. The output of NOR gate 295 is directly connected to the cathode of a diode 320; and the anodes of diodes 318 and 320 are connected together and to the second lowermost input of NAND gate 326 by a conductor 324. A resistor 322 connects the conductor 324 to the source of regulated plus 12 volts DC.

The output of the NAND gate 326 is connected to the input of a RELAY DRIVER 330, and also to the upper input of NAND gate 328. Although different relay drivers could be used, a simple transistor stage which responds to a O at the input thereof to provide a 1 at the output thereof and which responds to a l at the input thereof to provide a 0 at the output thereof is quite usable. A conductor 332 extends from the output of relay driver 330 to a MOTOR AND RELAY sub-block 360 within the MOTOR CONTROLLING block 354. The output of NAND gate 328 is directly connected to the lower input of NAND gate 326 and, by a cnductor 334, to the second-lowermost inputs of NAND gates 728 and 730 in the INHIBIT LOGIC block 718.

As shown particularly by FIG. 7, the OVERLEVEL SENSING sub-block 296 has a resistor 336 which connects the conductor 791 to the base of an NPN transis' tor 338. The emitter of that transistor is connected to the junction of resistors 350 and 352 which constitute a voltage divider that is connected between ground and the source of regulated plus twelve volts DC. A iode 340 has the anode thereof connected to the conductor 77 8; and has the cathode thereof directly connected to the emitter of a PNP transistor 346 and, by seriesconnected resistors 342 and 344, to the collector of transistor 338. The junction between the resistors 342 and 344 is connected to the base of transistor 346. A resistor 348 is connected between the collector of transistor 346 and ground; and that collector also is connected to conductor 297.

Conductors 368 and 370 extend from the MOTOR AND RELAY sub-block 360 to a SPEED ADJUSTING sub-block 356. As shown particularly by FIG. 5, the latter sub-block includes a full wave diode bridge 376; and conductor 368 is connected to one of the AC. terminals of that bridge, and the conductor 370 is connected to the other of those A.C. terminals. One of the DC. terminals of that bridge is grounded, and the other of those D.C. terminals is connected to the base of an NPN transistor 378 by a resistor 380. A resistor 382 is connected between ground and the base of that transistor; and the emitter of that transistor is grounded. The

collector of that transistor is connected to the source of regulated plus 12 volts DC. by a resistor 384.

A capacitor 386 is connected between the collector of transistor 378 and terminal 2 of a MONOSTABLE MULTIVIBRATOR 392. Although different monostable multivibrators could be used, the NE 555V monostable multivibrator made by the Signetics corporation has been found to be very useful. A diode 388 has the anode thereof connected to the right-hand terminal of capacitor 386, and has the cathode thereof connected to the regulated source of plus 12 volts DC; and a resistor 390 is connected in parallel with that diode. Terminal 1 of the monostable multivibrator 392 is directedly connected to ground, terminal 8 is directly connected to the regulated source of plus 12 volts DC, and terminals 6 and 7 are connected together and to a junction between a resistor 398 and a capacitor 396 which are connected between ground and that regulated source of plus 12 volts D.C. Terminal of that monostable multivibrator is connected to ground by a capacitor 394; and terminal 4 is connected to ground by a capacitor 410. The latter terminal also is connected to the regulated source of plus 12 volts D.C. and to the upper terminal of a resistor 400. That resistor and a resistor 402 are connected in series between ground and the regulated source of plus 12 volts D.C. Terminal 3 of the monostable multivibrator 392 is connected to the base of an NPN transistor 414 by a resistor 412. The emitter of that transistor is directly connected to ground, and the collector of that transistor is connected to the junction between resistors 400 and 402. A resistor 404, a potentiometer 408 and a resistor 406 constitute a voltage divider which is connected between ground and the regulated source of plus 12 volts DO; and the movable Contact of that potentiometer is connected to the inverting terminal of an amplifier 420. Although different amplifiers could be used, an MC 1741 Motorola amplifier has been found to be very useful. A resistor 416 is connected between the collector of transistor 414 and the non-inverting input of amplifier 420; and a capacitor 418 is connected between that non-inverting input and ground. One of the terminals of the amplifier 420 is directly connected to ground; and another of those terminals is directly connected to an un-regulated source of plus 24 volts DC, and is connected to ground by a capacitor 422. A capacitor 424 is connected between the output and the inverting terminal of the amplifier 420; and a series-connected capacitor 426 and resistor 428 also are connected between that output and that inverting terminal.

A Zener diode 430, a resistor 432, and a conductor 364 connect the output of amplifier 420 to the collector of an NPN transistor 466, to the anode of a diode 470, and to the base of an NPN transistor 468 which are in the SPEED MAINTAINING sub-block 358 as shown by FIG. 6. The emitter of transistor 466 is directly connected to ground, the cathode of diode 470 is connected to ground by a resistor 472, and the emitter of transistor 468 is connected to ground by a resistor 479. A two-input NAND gate 434 has those inputs connected together to enable that NAND gate to act as an inverter; and those inputs are connected to the conductor 253. The output of that NAND gate is connected to the base of an NPN transistor 438 by a resistor 436. The emitter of that transistor is directly grounded, and the collector of that transistor is connected to the cathodes of diodes 442 and 444. A resistor 440 connects the anode of diode 442 to the regulated source of plus 12 volts DC; and the anode of diode 444 is directly connected to the upper inputs of two-input NAND gates 448 and 450', and is connected to the regulated source of plus 12 volts DC. by a resistor 446. A resistor 452 and a capacitor 454 constitute a series RC circuit which is connected between ground and the regulated source of plus 12 volts DC; and the junction between that resistor and that capacitor is connected to the lower input of NAND gate 448. A diode 456 has the anode thereof connected to the output of NAND gate 448; and it has the cathode thereof connected to the lower input of NAND gate 450 by a resistor 462. A capacitor 458 and a resistor 460 constitute a parallel-connected RC circuit which is connected between ground and the cathode of diode 456. The output of NAND gate 450 is connected to the base of transistor 466 by a resistor 464. A resistor 478 connects the collector of transistor 468 to the cathode of a diode 476 and to the base of a PNP transistor 480. A resistor 474 connects the anode of diode 476 to the regulated source of plus 24 volts DO; and a resistor 484 connects the emitter of transistor 480 to that regulated source. Resistors 486 and 488 connect the collector of transistor 480 to a conductor 366 which extends to the MOTOR AND RELAY sub-block 360 of FIG. 8. The junction between those resistors is connected to the base of an NPN transistor 482; and the collector of that transistor is connected directly to the regulated source of plus 24 volts DC, and the emitter of that transistor is directly connected to the conductor 366.

As shown particularly by FIG. 8, the conductor 366 is connected to a movable relay contact 492, to the cathode of a diode 496 and to one terminal of a capacitor 498. The anode of diode 496, the other terminal of capacitor 498, and a movable relay contact 494 are connected together and to a conductor 372 which extends to a CURRENT SENSING sub-block 362. The forward stationary relay contact 492 is connected to the upper terminal of motor 562, and the reverse stationary relay contact 492 is connected to the lower terminal of that motor. The forward stationary relay contact 494 is connected to the lower terminal of motor 562, and the reverse stationary relay contact 494 is connected to the upper terminal of that motor. The coil which controls the movable relay contacts 492 and 494 is denoted by the numeral 490; and one terminal of that coil is connected to the regulated source of plus 24 volts D.C., while the other terminal of that coil is connected to the conductor 332. One terminal of the A.C. generator 560 is connected to the conductor 370, while the other terminal of that A.C. generator is connected to the conductor 368.

The conductor 372 is connected to the base of an NPN transistor 500 by series-connected resistors 504 and 508. A resistor 502 is connected between ground and the junction between conductor 372 and resistor 504; and a resistor 506 is connected between ground and the junction between resistors 504 and 508. The emitter of transistor 500 is grounded; and the collector of that transistor is directly connected to the input of an inverter 512, and is connected to the regulated source of plus 12 volts DC. by a resistor 510.

The output of the inverter 512 is connected to a conductor 374 which extends to the uppermost input of a four-input NOR gate 518 in a COUNT ENABLE block 514. One branch of conductor 776 is connected to the second lowermost input of that NOR gate, and one branch of conductor 780 is connected to the lowermost input of that NOR gate. A branch of conductor 778 is connected to the lower input of a BORDER subblock 516, and a branch of conductor 791 is connected to the upper input of that sub-block. The output of that sub-block is connected to the second uppermost input of NOR gate 518 by a conductor 517. The output of that NOR gate is connected to the input of an inverter 520; and the output of that inverter is connected to the lower input of two-input NOR gates 800 and 802 in the VALIDATING AND VENDING LOGIC block 784 by a conductor 522.

As shown particularly in FIG. 4 the BORDER subblock 516 has a resistor 684 which connects the conductor 791 to the base of an NPN transistor 682. Resistors 688 and 690 constitute a voltage divider connected between ground and the regulated source of plus 12 volts D.C.; and the junction between those resistors is connected to the emitter of transistor 682. A resistor 686 connects the collector of that transistor to the regulated source of plus 12 volts D.C. A resistor 692 connects the collector of transistor 682 to the upper inputs of two-input NANd gates 696 and 700. A capacitor 694 is connected between ground and the junction between resistor 692 and those upper inputs; and that capacitor will by-pass to ground any high frequency pulses, on conductor 791, such as transients and motor noise. The output of NAND gate 696 is connected to the lower input of NAND gate 700 and also to the upper input of a two-input NAND gate 698. The lower input of NAND gate 698 is connected to a branch of conductor 778. The output of NANd gate 698 is connected to the lower input of NANd gate 696, and also to the lower input of a two-input NOR gate 708. The anode of a diode 702 is connected to the output of NANd gate 700; and the cathode of that diode is connected to the interconnected inputs of a twoinput NOR gate 704 which serves as an inverter. A resistor 710 and a capacitor 712 constitute a parallel-connected R.C. network connected between ground and the interconnected inputs of NOR gate 704. The output of NOR gate 704 is connected to the cathode of a diode 713', and the anode of that diode is connected to the upper input of a twoinput NOR gate 706. A resistor 714 and a capacitor 716 constitute a series-connected R.C. circuit connected between ground and the source of regulated plus 12 volts D.C.; and the junction between that resistor and that capacitor is connected to the anode of diode 7113, and to the upper input of NOR gate 706. The output of NOR gate 708 is connected to the lower input of NOR gate 706; and the output of NOR gate 706 is connected to the upper input of NOR gate 708 and also to the conductor 517.

The numeral 524 denotes a COUPLING block in FIG. 3B; and that block has terminals 526, 528 and 530 which are connectable to a dispensing machine such as a change-making machine. In one preferred embodiment of the present invention, the terminal 526 is connected to a circuit of a dispensing machine which can selectively indicate that dollar bills should not be accepted, and the terminal 530 is connected to a circuit in that dispensing machine which can selectively indi cate that dollar bills should not be accepted. The terminal 528 is connected to a common conductor from that dispensing machine. A resistor 532 is connected between the terminal 526 and the anode of a diode 536; and a resistor 534 is connected between the terminal 530 and the anode of a diode 538. The chathodes of the diodes 536 and 538 are connected together and to the common terminal 528. an opto-coupler 540 is connected in parallel with the diode 536 and an opto-coupler 542 is connected in parallel with the diode 538. The emitters of the light-sensitive elements in those opto-couplers are connected together and to ground. The collector of the light-sensitive element in opto-coupler 540 is directly connected to the cathode of a diode 548, and is connected to'the source of regulated plus 12 volts D.C. by a resistor 544. The collector of the light sensitive element in the opto-coupler 542 is directly connected to the cathode of a diode 550, and is connected to the source of regulated plus 12 volts D.C. by a resistor 546. A resistor 552 and a capacitor 556 are connected in series between the source ofregulated plus 12 volts D.C. and ground; and the junction between that resistor and that capacitor is connected to the anode of diode 548, and also to a conductor 566 which extends to the INHIBIT LOGIC block 718. A resistor 554 and a capacitor 558 are connected in series between the source of regulated 12 volts D.C. and ground; and the junction between that resistor and capacitor is connected to the anode of diode 550 and to a conductor 568 which extends to that INHIBIT LOGIC block.

The conductor 566 is connected to the upper input of a two-input NAND gate 720 and also to the input of v an inverter 724. The conductor 568 is connected to the lower input of NAND gate 720, and also to the input of an inverter 726. The output of NAND gate 720 is connected to the input of an inverter 722; and the output of that inverter is connected to a conductor 732 which extends to the SWITCH LOGIC block 738. The output of inverter 724 is connected to the lowermost input of NAND gate 728; and the output of inverter 726 is connected to the lowermost input of NAND gate 730. The output of NAND gate 728 is connected to a conductor 736 which extends to the VALIDATING AND VENDING LOGIC block 784; and the output of NAND gate 730 is connected to a conductor 734 which also extends to that block.

The movable contacts of the switches 146, 156 and 162 are connected together and to ground, as shown by FIG. 3B. A resistor 740 connects the stationary contact of switch 146 to the source of regulated plus 12 volts D.C.; and a resistor 746 connects that stationary contact to the lower input of a three-input NOR gate 758. A capacitor 752 is connected between ground and the junction between resistor 746 and that lower input. A resistor 742 connects the stationary contact of switch 156 to the source of regulated plus 12 volts D.C.; and a resistor 748 connects that stationary contact to the conductor 766 and also to the input of an inverter 772. The output of that inverter is connected tothe conductor 778. A capacitor 754 is connected between ground and the junction of resistor 748, conductor 766, and the input of inverter 772. A resistor 744 connects the stationary contact of switch 162 to the source of regulated plus 12 volts D.C.; and a resistor 750 connects that stationary contact to the lower input of a two-input NOR gate 760. A capacitor 756 is connected between ground and the junction between resistor 750 and that lower input. The inverter 762 has the output thereof connected to the upper input terminals of NOR gate 758 and 760; and the middle input terminal of NOR gate 758 is connected to the conductor 732. The output of NOR gate 758 is connected to conductor 764 and to the input of an inverter 770; and the output of that inverter is connected to conductor 776. The output of NOR gate 760 is connected to conductor 768 and to the input of an inverter 774; and the output of that inverter is connected to conductor 780.

A constant current diode 786 in FIG. 3C connects one terminal of the magnetic head 208 to the source of regulated plus l2 volts D.C. Although different constant current diodes could be used, a 1N5297 constant current diode has been found to be very useful. The other terminal of magnetic head 208 is connected to one terminal of magnetic head 210; and the other terminal of the latter magnetic head is connected to ground by a resistor 788. An amplifier 790 has one input terminal thereof connected to the junction between the cathode of constant current diode 786 and the upper terminal of magnetic head 208, and has the other terminal thereof connected to the junction between resistor 788 and the lower terminal of magnetic head 210. The output of amplifier 790 is connected to conductor 791. One branch of that conductor is connected to the input of a FREQUENCY DETECTOR sub-block 792, and another branch of that conductor is connected to the input of a FREQUENCY DETEC- TOR sub-block 794. As shown particularly by FIG. 9, the FREQUENCY DETECTOR sub-block 792 includes a phase locked loop 854. One very useful phase locked loop is the NE567V phase locked loop of the Signetics Corporation. A resistor 856 and a capacitor 862 connect the conductor 791 to terminal 3 of the phase locked loop 854. Oppositely polarized diodes 858 and 860 are connected between ground and the junction between resistor 856 and capacitor 862. A potentiometer 878 has one terminal thereof connected to pin 5 of the phase locked loop 854 and has the other terminal thereof connected to pin 6 of that phase locked loop by a fixed resistor 880. The movable contact of that potentiometer is connected to the junction between that potentiometer and that resistor to enable that potentiometer to serve as an adjustable resistor. A capacitor 882 is connected between ground and the junction between resistor 880 and pin 6 of the phase locked loop 854. A conductor 876 directly connects pin 7 of that phase locked loop to ground; and a conductor 864 connects pin 4 of that phase locked loop to a source of regulated plus 6 volts DC. A capacitor 866 connects pin 2 of that phase locked loop to ground; and a conductor 795 is connected to pin 8 of that phase locked loop. A resistor 867 and a conductor 868 connect pin 1 of the phase locked loop to the source of regulated plus 6 volts D.C.; and a capacitor 870 connects that pin to ground. A resistor 872 and a capacitor 874 connect pin 1 to pin 8 of that phase locked loop.

The-FREQUENCY DETECTOR 794 is identical to the FREQUENCY DETECTOR 792 in all respects other than the value of the resistor 880. Thus, in the said preferred embodiment of the present invention, each of the FREQUENCY DETECTOR sub-blocks 792 and 794 has a 2,200 ohm resistor 856, has 1N914 diodes 858 and 860, has a one-tenth microfarad capacitor 862, has a 22/100 of a microfarad capacitor 866, has a 10,000 ohm potentiometer 878, has a 68/l,000 of a microfarad capacitor 882, has a two and twotenths microfarad capacitor 870, has a 100,000 ohm resistor 867, has a 100 ohm resistor 872, and has a 22/100 of a microfarad capacitor 874. The FRE- QUENCY DETECTOR sub-block 792 differs from the FREQUENCY DETECTOR sub-block 794 in having a 7,500. ohm resistor 880, whereas the latter FRE- QUENCY DETECTOR sub-block has a fourteen thousand seven hundred ohm resistor 880.

The conductor 795, which is connected to the output of FREQUENCY DETECTOR sub-block 792, is connected to the upper input of NOR gate 800; and a conductor 797, which is connected to the output of FRE- QUENCY DETECTOR sub-block 794, is connected to the upper input of NOR gate 802. A resistor 796 extends between conductor 795 and the source of regulated plug 12 volts D.C.; and a resistor 798 extends between the conductor 797 and that regulated source. The output of NOR gate 800 is connected to the clock input of a counter 804. While different counters could be used, an RCA 4015 Shift Register has been found to be very useful. The output of NOR gate 802 is connected to the clock input of a similar counter 806.

A stationary switch contact 812 and a stationary switch contact 818 are connected together and to the fourth output terminal of counter 804. Stationary switch contacts 814 and 816 are connected, respectively, to the second and third output terminals of that counter. A movable switch contact 808 and a movable switch contact 810 are ganged together; and those movable switch contacts coact with the stationary switch contacts 812, 814, 816 and 818 to constitute a two-pole, double-throw switch. In the position shown by Flg. 3C, movable contact 808 is in engagement with stationary contact 814 and movable contact 810 is in engagement with stationary contact 818. The movable contact 808 is connected to the upper input of a twoinput NAND gate 834; and a conductor connects the third output terminal of counter 804 to the lower input of that NAND gate. The movable contact 810 is connected to the input of an inverter 819; and the output of that inverter is connected to the data input of the counter 804. The conductor 736 is connected to the reset terminal of the counter 804.

A stationary switch contact 824 and a stationary switch contact 830 are connected together and to the fourth output terminal of counter 806. Stationary switch contacts 826 and 828 are connected, respectively, to the second and third output terminals of that counter. A movable switch contact 820 is connected to the upper input of a two-input NAND gate 836; and a conductor extends from the third output terminal of that counter to the lower input of that NAND gate. A movable switch contact 822 is connected to the input of an inverter 832; and the output of that inverter is connected to the data input of counter 806. The movable contacts 820 and 822 coact with the stationary contacts 824, 826, 828 and 830 to define a twopole, double-throw switch. In the position shown by FIG. 3C, movable contacts 820 and 822 are in engagement, respectively, with stationary contacts 826 and 830. The conductor 734 is connected to the reset terminal of the counter 806.

The output of NAND gate 834 is connected to the upper input of NOR gate 838, and also to the input of an inverter 844. The output of NAND gate 836 is connected to the upper input terminal of NOR gate 840, and also to the input of an inverter 842. The outputs of inverters 842 and 844 are connected, respectively, to

the upper and lower inputs of an EXCLUSIVE OR gate 846. The output of that EXCLUSIVE OR gate is connected directly to the conductor 850 and to the input of an inverter 848; and the output of that inverter is connected to the conductor 852. The output of NOR gate 838 is connected to the input of a RELAY DRIVER 884; and the output of NOR gate 840 is connected to the input of a RELAY DRIVER 886. The RELAY DRIVERS 884 and 886 could be of different types; but, in the said one preferred embodiment those relay drivers are simple transistor stages which respond to Os at the inputs thereof to provide ls at the outputs thereof, and which respond to ls at the inputs thereof to provide Os at the outputs thereof. The output of RELAY DRIVER 884 is connected to one terminal of a relay coil 888; and the output of the RELAY DRIVER 886 is connected to one terminal of a relay coil 890. The other terminals of those relay coils are connected together and to the source of regulated plus 24 volts D.C. Those relay coils control contacts, not shown, in the dispensing machine, vending machine or other device with which the paper currency validator of the present invention is associated.

At-rest Condition of Paper Currency Validator: In the at-rest condition of the paper currency validator, each of the switches 146, 156 and 162 is open; and hence a binary 1 will appear at the lower inputs of NOR gates 758 and 760, on conductor 766, and at the input of inverter 772. This means that a binary will appear on conductors 764, 768 and 778, and that a I will appear on conductors 776 and 780. The NAND gate 232 in the START AND RUN LOGIC block 230 in FIG. 3A will respond to the ls at the inputs thereof to apply a 0 to the conductor 234; and the inverter 238 will respond to the resulting O at the input thereof to apply ls to the upper input of NAND gate 240 and to the cathode of diode 245. The resulting back biasing of that diode will cause a l to appear at the upper input of NAND gate 251. The COUNTERS 804 and 806 in FIG. 3C will have Os at the output terminals thereof; and NAND gates 834 and 836 will respond to the resulting Os at the inputs thereof to apply Is to the upper inputs of NOR gates 838 and 840 and to the inputs of inverters 842 and 844. The resulting application of 0s to both inputs of the EXCLUSIVE OR gate will cause that EXCLUSIVE OR gate to apply a O to conductor 850 and to the input of inverter 848; and that inverter will apply a l to conductor 852 and hence to the lower inputs of NAND gate 268 and of NOR gate 288.

The 0 on conductor 850 will cause NAND gate 248 in FIG. 3A to apply a l to conductor 242, and thus to the lower input of NAND gate 251. The ls at both inputs of the latter NAND gate will cause that NAND gate to apply a O to conductor 253, and thus to the interconnected inputs of NAND gate 434 in the SPEED MAINTAINING sub-block of FIG. 6. The resulting l at the output of NAND gate 434 will be applied to the base of transistor 438, and will render that transistor conductive and cause it to apply a 0 to the cathode of diode 444. The resulting forward biasing of that diode will apply 0 to the upper inputs of NAND gates 448 and 450; and the resulting l s at the outputs ofthose NAND gates will forward bias diode 456 and transistor 466. The source of regulated plus 12 volts DC. will apply a l to the lower input of NAND gate 448. Capacitor 458 will respond to the forward biasing of diode 456 to charge up to a voltage close to 12 volts, and thereby will apply a l to the lower input of NAND gate 450. Transistor 466 will become conductive and will thereby apply a 0 to the base of transistor 468 to render the latter transistor non-conductive; and the resulting l at the base of transistor 480 will keep that transistor nonconductive. Consequently, a 0 will appear at the base of transistor 482 to render that transistor. nonconductive; and hence current will not flow through conductor 366 and motor 562. As a result, that motor and the movable parts of the bill transport will remain at rest.

The constant current diode 786 in FIG. 3C will permit a fixed value of direct current to flow through the serially connected magnetic heads 208 and 210, and thereby will provide a DC. bias in those heads. However, in the at-rest condition of the paper currency validator, those magnetic heads and the amplifier 790 will cause a O to appear on conductor 791. The transistor 338 in the OVERLEVEL SENSING sub-block 296 of FIG. 7 will be kept non-conductive by the 0 at the base thereof, and hence transistor 346 also will be kept non-conductive. As a result, the collector of transistor 346 will permit 0 to appear on conductor 297, and hence at the upper input of NOR gate 295.

The O on conductor 791 also will be applied to the inputs of FREQUENCY DETECTORS 792 and 794; and those FREQUENCY DETECTORS will respond to those Os to permit Is to appear at the outputs thereof. As a result I will appear at the upper input of each NOR gate 800 and 802.

The l on conductor 242 also will be applied to the input of inverter 264 with a consequent application of a 0 to the upper input of NAND gate 266. In addition, the l on conductor 242 will be applied to the inverter 762 in FIG. 3B with consequent application of Os to the upper inputs of NOR gates 758 and 760, and to the lower inputs of NOR gates 838 and 840 in FIG. 3C; and those NOR gates will respond to that l or to the ls which the NAND gates 834 and 836 apply to the lower inputs thereof to apply Os to the inputs of RELAY DRIVERS 884 and 886. Those RELAY DRIVERS will apply ls to the left-hand terminals of relay coils 888 and 890; and hence those relay coils will remain unenergized.

The PULSE GENERATOR 252 in FIG. 3A will be applying steep-sided, flat-topped pulses to the count" terminal of the BINARY COUNTER 254 at a frequency of Hertz; but NAND gate 246 will respond to the 1 on conductor 766 and to the l on conductor 242 to apply a 0 to the lower input of NAND gate 248. Although the source of regulated plus 12 volts applies a 1 to the upper input of NAND gate 248, the 0 at the lower input of that NAND gate will cause that NAND gate to apply a l to the reset terminal of BINARY COUNTER 254. As long as l is applied to that reset terminal, 0 will appear on all of the conductors 256, 258 and 260; and hence at the lower input of NAND gate 266, at the upper and middle inputs of NAND gate 268, at the upper input of NAND gate 270, and at all of the inputs of NAND gate 272. Those NAND gates will respond to those ()s to develop ls at the outputs thereof. Inverter 274 will respond to the l at the output of NAND gate 272 to apply a 0 to the anode of diode 276--thereby back biasing that diode, and thus permitting 0 to appear on conductor 284 and hence at the upper input of NOR gate 295. The l on conductor 776 and the l on conductor 780 will cause NOR gates 288 and 290 to apply to the anodes of diodes 298 and 300 thereby back-biasing those diodes, and thus permitting 0 to appear on conductor 284 and hence at the upper input of NOR gate 295. The l on conductor 776 and the l on conductor 766 will cause the NOR gates 292 and 294 to apply Os to the middle and lower inputs of NOR gate 295; and hence that NOR gate will apply a l to the cathode of diode 320 with consequent back-biasing of that diode and the resulting application of a l to the second lowermost input of NAND gate 326. The transistor 302 will be conductive, and hence will be applying 0 to the input of inverter 314; and that inverter will apply a l to the cathode of diode 312 with consequent back-biasing of that diode and a resulting uninterrupted application of a 1 to the second lowermost input of NAND gate 326.

The 0 on conductor 234 will cause NAND gate 328 in the MOTOR REVERSE LOGIC block 286 in FIG. 3A to apply a l to the lowermost input of NAND gate 326; and the Is at the outputs of NAND gates 268 and 270 will be applied to the uppermost and second uppermost inputs of NAND gate 326. As a result, that NAND gate will apply a O to the input of RELAY DRIVER 330 with the consequent application of a l to the lefthand end of relay coil 490 in FIG. 8 causing that coil to remain de-energized and to permit the movable relay contacts 492 and 494 to remain in their forward positions. NAND gate 326 also will apply a 0 to the upper input of NAND gate 328.

The dispensing machine, with which the paper currency Validator is associated, will be applying ls to the terminals 526 and 530 of the COUPLING block 524 in FIG. 3B; and hence the light-emitting diodes within the opto-couplers 540 and 542 will be emitting light. The light-sensitive elements of those opto-couplers will respond to that light to be conductive, and hence 0 will be applied to the cathodes of the diodes 548 and 550. The resulting forward biasing of those diodes will cause 0 to be applied to the upper and lower inputs of NAND gate 720 and also to the inputs of inverters 724 and 726. Those inverters will apply ls to the lowermost inputs of NAND gates 728 and 730. The 1 at the output of NAND gate 266 of the TIMER LOGIC block 262 in FIG. 3A will appear at the second uppermost inputs of NAND gates 728 and 730, the 1 at the output of NAND gate 328 in the MOTOR REVERSE LOGIC block 286 in FIG. 3A will appear at the second lowermost inputs of NAND gates 728 and 730, and the l at the output of inverter 314 in that block will appear at the uppermost inputs of NAND gates 728 and 730. As a result Os will appear at the outputs of those NAND gates, and hence at the reset terminals of COUNT- ERS 804 and 806 in the VALIDATING AND VEND- ING LOGIC block 784 in FIG. 3C. The l at the output of NAND gate 720 will cause inverter 722 to apply a O to the middle input of NOR gate 758.

The O on conductor 791 will be applied to the base of transistor 682 in the BORDER sub-block 516 in FIG. 4; and the resulting non-conductive state of that transistor will enable ls to appear at the upper inputs of NAND gates 696 and 700. The 0 on conductor 778 will be applied to the lower input of NAND gate 698; with a consequent l at the output of that NAND gate' and hence at the lower inputs of NAND gate 696 and of NOR gate 708. That NOR gate will apply a O to the lower input of NAND gate 706. NAND gate 696 will apply a 0 to the upper input of NAND gate 698, and

also to the lower input of NAND gate 700; and the resulting l at the output of the latter NAND gate will forward bias diode 702 and thereby charge capacitor 712 and apply a l to the interconnected inputs of NOR gate 704. That NOR gate will apply a O to the cathode of diode 713 to forward bias that diode; and hence capacitor 716 will be discharged, and NOR gate 706 will have Os at both inputs thereof, and thus will apply a l to the upper input of NOR gate 708 and also to conductor 517. That conductor will apply that l to the second uppermost input of NOR gate 518 and will thereby cause that NOR gate to apply a 0 to the input of inverter 520 with consequent application of a l to the lower inputs of NOR gates 800 and 802 in the VALIDATION AND VENDING LOGIC block 784 in FIG. 3C.

The l on conductor 776 will be applied to the second lowermost input of-.NOR gate 518, the 0 on conductor 764 will be applied to the upper inputs of NOR gates 290 and 294, the O on conductor 768 will be applied to the middle input of NOR gate 288 and to the lower input of NOR gate 294, and the 0 on conductor 778 will be applied to the middle input of NOR gate 292. The l on conductor 780 will be applied to the lower inputs of NOR gates 292 and 518 and of NAND gate 270, and the 0 on conductor 850 will be applied to the lower input of NOR gate 290. The CURRENT SENSING sub-block 362 will be applying a l to the uppermost input of NOR gate 518.

Operation of Paper Currency Validator by Authentic US. 1 Dollar Bill: If an authentic US. 1 dollar bill is disposed adjacent the platform 32 of the bill transport 30 of FIG. 1 so the black-ink face thereof is up and so the bottom of the portrait of George Washington is close to the flange 142 on the cover 140, the upper portion of the portrait background will be in register with the magnetic head 208 and the lower portion of that portrait background will be in register with the magnetic head 210, as indicated by FIG. 2. If the leading edge of that bill is moved far enough inwardly of that bill transport, it will cause the actuator 148 of switch 146 to move far enough to close that switch; and, thereupon, the 1 at the lower input of NOR gate 758 in the SWITCI-I LOGIC block 738 will change to 0. Immediately, the output of that NOR gate will change to l with a consequent l on conductor 764 and a consequent 0 on conductor 776. The resulting l at the upper input of NOR gate 294 will not be effective at this time because the 1 at the middle input of that NOR gate had been maintaining 0 at the output of that NOR gate. Similarly, the resulting 1 at the upper input of NOR gate 290 will not be effective at this time because the I at the middle input of that NOR gate had been keeping 0 at the output of that NOR gate. The resulting 0 at the second lowermost input of NOR gate 518 will not be significant at this time because the ls at the second uppermost and bottom inputs will be maintaining 0 at the output of that NOR gate. The resulting O at the upper input of NOR gate 292 will not be significant at this time because the l at the lower input will be maintaining a O at the output of that NOR gate. Similarly, the resulting 0 at the upper input of NOR gate 288 will not be significant at this time because the l at the lower input will be maintaining a 0 at the output of that NOR gate. However, the resulting 0 at the upper input of NAND gate 232 will cause a l to appear at the output of that NAND gate and hence on conductor 234. The resulting application of l to the lower input of NAND gate 328 will not be significant at this time because the at the upper input of that NAND gate will maintain l at the output of that NAND gate. However, the application of l to the input of inverter 238 in the VEND ENABLE LOGIC block 236 will cause that inverter to apply a 0 to the cathode of diode 245 and to the upper input of NAND gate 240. The 0 at the upper input of that NAND gate will not change the output of that NAND gate because conductor 850 has been applying a 0 to the lower input of that NAND gate; but the 0 at the cathode of diode 245 will forward bias that diode, and will thereby apply a O to the upper input of NAND gate 251. The resulting application of I to the interconnected inputs of NAND gate 434 in the SPEED MAIN- TAINING subblock 358 of the MOTOR CONTROL- LING block 354 will cause that NAND gate to apply 0 to the base of transistor 438, thereby rendering that transistor non-conductive. The resulting l at the oathode of diode 444 will back-bias that diode, and hence will enable the source of regulated plus twelve volts DC. to apply ls to the upper inputs of NAND gates 448 and 450. The resulting zero at the output of NAND gate 448 will back-bias diode 456, and thereby permit capacitor 458 to start discharging through resistor 460. However, that capacitor normally requires about eighteen seconds to discharge; and, during that length of time, it will continue to apply a l to the lower input of NAND gate 450. The I at the upper input of NAND gate 450 will cause that NAND gate to apply a 0 to the base of transistor 466, thereby rendering that transistor non-conductive. At such time, current will flow from the output of amplifier 420 in the SPEED ADJUSTING sub-block 356 of the MOTOR CONTROLLING block 354 via Zener diode 430, resistor 432, conductor 364, the baseemitter circuit of transistor 468 in SPEED MAINTAINING sub-block 358, and resistor 479 to ground; and that flow of current will render that transistor conductive. The resulting drop in the voltage at the junction of diode 476 and resistor 478 in that subblock will render transistor 480 conductive; and, thereupon, current will flow through the base-emitter circuit of transistor 482 and render that transistor conductive. At such time, current will flow from the source of regulated plus 24 volts D.C. via transistor 482, conductor 366, the movable and left-hand relay contacts 492 in the MOTOR AND RELAY sub-block 360, motor 562, the left-hand and movable relay contacts 494, conductor 372, and in part to ground through resistor 502 in the CURRENT SENSING sub-block 362 and in part to ground through resistors 504 and 506. The motor 562 will start rotating in the forward direction, and the output shaft 203 thereof will rotate worm gear 202, worm wheel 200, and shaft 182; and the belt 198 and its counterpart belt will move the lower runs thereof to the right in FIG. 1, and will thereby move the bill inwardly of the bill transport. The motor 562 will drive those belts, and hence each inserted bill, at the rate of ten inches per second.

After the leading edge of the bill has been moved approximately one-half of an inch further inwardly of the bill transport by the belt 198 and its counterpart, the actuator 158 of the switch 156 will have been moved far enough to close that switch. Thereupon, 0 will appear on conductor 766 and 1 will appear on conductor 778. The resulting 0 at the middle input of NAND gate 232 in the START AND RUN LOGIC block 230 will not be significant at this time, because switch 146 remains closed and thereby maintains l at'the output of that NAND gate. Similarly, the resulting 0 at the middle input of NOR gate 294 will not be significant at this time, because a 1 appears at the upper input of that NOR gate. However, the 0 at the lower input of NAND gate 246 will change the output of that NAND gate to I, and thereby will cause NAND gate 248 to remove the I from the reset input of BINARY COUNTER 254; and, thereupon, that counter will begin to count the pulses from the PULSE GENERATOR 252.

The application of a l to the middle input of NOR gate 292 is not significant at this time bacause the l at the bottom input of that NOR gate is maintaining 0 at the output of that NOR gate. The application of a I to the anode of the diode 340 in the OVERLEVEL SENS- ING sub-block 296 of FIG. 7 will forward bias that diode; but the 0 at the base of transistor 338 will keep that transistor non-conductive, and will thereby act to keep transistor 346 non-conductive. Consequently, 0 will continue to appear at the output of that OVER- LEVEL SENSING sub-block. The application of l to the lower input of NAND gate 698 in the Border subblock 516 of FIG. 4 will not be effective at this time, because the NAND gate 696 will continue to apply 0 to the upper input of NAND gate 698. Consequently, the motor 562 will cause belt 198 and its counterpart to continue to move the bill inwardly of the paper currency validator, and the BINARY COUNTER 254 will begin counting.

During each operation of the paper currency valida- I tor, a number of events must occur within closely controlled, individually different time periods or the motor 562 will reverse and will cause the belt 198 and its counterpart to move the inserted bill back out through the front of the bill transport. For example, the switch 162 must close within 535 milliseconds after the switch 156 is closed, a validation signal must be developed within 668 milliseconds after switch 156 is closed, and switch 156 must re-open within 735 milliseconds after it is closed. Also, a time period of 134 milliseconds must have been developed by the time switch 162 reopens if a validation signal is present. Those various time periods are established by the TIMER block 244 and by the TIMER LOGIC block 262. I

The BINARY COUNTER 254 in TIMER block 244 will apply a l to conductor 256 whenever the total count therein is 4 through 7, l2 through 15, 20 through 23,28 through 31, 36 through 39, and 44. That counter will apply a l to conductor 258 whenever the total count therein is 8 through 15, 24 through 31, and 40 through 44; and it will apply a l to conductor 260 whenever the total count therein is 32 through 44.

The BINARY COUNTER 254 will increase the total count therein each time it senses the negative-going edge of a pulse from the PULSE GENERATOR 252; and it will receive. such pulses at the rate of one every 16 7/10 milliseconds. Approximately 67 milliseconds after the switch 156 is closed, a 1 will appear on conductor 256 and will be applied to the upper input of NAND gate 272; but that I will not have any immediate effect because conductors 258 and 260 will continue to apply Us to the middle and lower inputs of that NAND gate. Approximately I34 milliseconds after switch 156 closes, the I on conductor 256 will change back to 0 and the 0 on conductor 258 will change to l. The resulting l at the lower input of NAND gate 266 is not significant at this time because inverter 264 continues to apply a to the upper input of that NAND gate. The resulting l at the upper input of NAND gate 268 is not significant at this time because conductor 260 continues to apply a 0 to the middle input of that NAND gate. The resulting l at the middle input ofv NAND gate 272 is not significant at this time because conductor 256 is applying a 0 to the upper input, and because conductor 260 is applying a 0 to the lower input, of that NAND gate.

Approximately 140 milliseconds after the switch 156 closed, the leading edge of the leading engraved border on the black-ink face of the bill will reach, and will start to move past, the air gap of the magnetic head 208. Thereupon, that magnetic head will apply pulses to the amplifier 790; and that amplifier will supply amplified pulses to the conductor 791.

Those amplified pulses will not have a frequency to which either of the FREQUENCY DETECTORS 792 and 794 is intended to respond; and hence those amplified pulses will not affect the ls at the outputs of those FREQUENCY DETECTORS. Those amplified pulses will be applied to the base of transistor 338 in the OVERLEVEL SENSING sub-block 296 of FIG. 7; but those amplified pulses will not have sufficient amplitude to render the transistor 338 conductive. Consequently, that OVERLEVEL SENSING sub-block will continue to permit 0 to appear on conductor 297. Those amplified pulses also will be applied to the base of transistor 682 in the BORDER sub-block 516 of FIG. 4; and the negative-going portions of those amplified pulses will make that transistor non-conductive, but the positive-going portions of those amplified pulses will render that transistor conductive. As a result, during the time period when the air gap of magnetic head 208 is sensing the leading border of the bill, the upper inputs of NAND gates 696 and 700 will see" a succession of alternating 0s and ls.

The first 0 which is applied to the upper input of NAND gate 696 will make the output of that NAND gate a l; and NAND gate 698 will respond to the resulting 1 at the upper input thereof and to the l which conductor 778 applies to the lower input thereof to apply a continuous 0 to the lower inputs of NOR gate 708 and of NAND gate 696. The NAND gates 696 and 698 thus act as an electronic latch which will maintainO at the lower input of NOR gate 708 and l at the lower input of NAND gate 700. The latter NAND gate will, in this way, be able to respond to the succession of alternating 0s and ls at the upper input thereof to apply a succession of 1s and Os to the anode of diode 702. Each 1 at that anode will forward-bias that diode and permit capacitor 712 to become charged; and each 0 at that anode will back-bias that diode and permit that capacitor to start discharging through resistor 710. However, the time constant of the RC network constituted by that capacitor and that resistor is about 60 milliseconds; and hence the rapidly-recurring forward-biasing of diode 702, in response to the amplified pulses from amplifier 790, will enable the charge on capacitor 712 to keep a l at the interconnected inputs of NOR gate 704. The resulting O at the output of that NOR gate will forward-bias the diode 713, thereby keeping capacitor 716 discharged and thereby applying a O at the upper input of NOR gate 706. The latter NOR gate will respond to the O at the lower input thereof, which has been maintained by the NOR gate 708, to apply a continuous 1 to the upper input of NOR gate 708 and to conductor 517. All of this means that as long as the leading border of the bill is in engagement with the air 2 gap of the magnetic head 208, the capacitor 712 will maintain a l at the interconnected inputs of NOR gate 704.

The leading edge of the leading border on the black ink face of the inserted bill will move into engagement with the air gap of the magnetic head 210 almost immediately after the trailing edge of that border moves beyond the air gap of the magnetic head 208; and the resulting amplified pulses from amplifier 790 will forward-bias and back-bias diode 702 in rapid succession. As a result, until the trailing edge of the leading border moves beyond the air gap of the magnetic head 210, the capacitor 712 will remain essentially fully charged, and thus will maintain a l at the interconnected inputs of NOR gate 704. In the preferred embodiment of the present invention, the magnetic heads 208 and 210 will respond to the leading border on the bill to cause the amplifier 790 to apply amplified pulses to the transistor 682 for approximately 90 milliseconds; and, during those 90 milliseconds, the voltage at the upper terminal of capacitor 712 will remain close to 12 volts.

Approximately 201 milliseconds after the switch 156 closed, and hence while the leading border of the bill was in engagement with the air gap of magnetic head 210, BINARY COUNTER 254 applied ls to conductors 256 and 258. However, because conductor 260 was still applying Os to the middle input of NAND gate 268 and to the lower input of NAND gate 272, and because conductor 242 was applying a l to the input of inverter 264 and thus was causing that inverter to apply a 0 to the upper input of NAND gate 266, the ls on conductors 256 and 258 were not significant at that time.

As soon as the trailing edge of the leading border on the black-ink face of the bill moves beyond the air gap of magnetic head 210, the capacitor 712 will start discharging through resistor 710. About 60 milliseconds later, the charge on that capacitor will have dissipated through that resistor to the point where the l at the interconnected inputs of NOR gate 704 becomes a 0. At such time, a 1 will appear at the output of that NOR gate; and that 1 will back-bias diode 713. Thereupon, capacitor 716 will start to charge; but the time constant of the RC network, constituted by that capacitor and by resistor 714, is about 30 milliseconds. Consequently, a 0 will continue to appear at the upperinput of NOR gate 706 for a-total of about 90 milliseconds after the trailing edge of the leading border moves out of engagement with the air gap of the magnetic head 210; and then that 0 will change to a 1.

Approximately milliseconds after the trailing edge of the leading border moves out of engagement with the air gap of the magnetic head 210, and hence approximately 20 milliseconds before the l on conductor 517 can become a 0, the leading edge of the bill will cause the actuator 164 of the switch 162 to move far enough to close that switch. In the said preferred embodiment of the present invention, the closing of switch 162 occurs approximately 300 milliseconds after the closing of switch 156. The resulting O at the lower input of NOR gate 760 will coact with the O at the upper input of that NOR gate to apply a 1 to conductor 768 and to the input of inverter 774 with a consequent application ofO to conductor 780. The l which will appear at the middle input of NOR gate 288 will not be significant at this time because conductor 852 is applying a 1 to the lower input of that NOR gate. Similarly, the resulting 1 at the lower input of NOR gate 294 is not significant at this time because conductor 764 is applying a l to the upper input of that NOR gate. The resulting at the lower input of NAND gate 232 is not significant to this time because conductors 766 and 776 are applying Os to the upper and middle inputs of that NAND gate; and the resulting 0 at the lower input of NAND gate 270 is not significant at this time because conductor 260 is applying a 0 to the upper input of that NAND gate. The resulting O at the middle input of NOR gate 290 is not significant at this time because conductor 764 is applying a l to the upper input of that NOR gate; and the resulting 0 at the lower input of NOR gate 292 is not significant at this time because conductor 778 is applying a l to the middle input of that NOR gate. The resulting 0 at the lowermost input of NOR gate 518 is not significant at this time because conductor 517, which extends from the BORDER subblock 516, is applying a l to the second uppermost input of that NOR gate.

Approximately milliseconds after switch 162 closed, and hence approximately 320 milliseconds after switch 156 closed, the charge on capacitor 716 in the BORDER sub-block 516 of FIG. 4 will increase to a value at which the O at the upper input of NOR gate 706 will change to a l. The resulting 0 on conductor 517 will be applied to the upper input of NOR gate 708 and to the second uppermost input of NOR gate 518. The 0 at the second uppermost input of NOR gate 518 will coact with the Os at all of the other inputs of that NOR gate to cause that NOR gate to apply a l to the input of inverter 520; and the resulting O at the output of that inverter will be applied to the lower inputs of NOR gates 800 and 802. However, the outputs of those NOR gates will remain 0 because ls appear at the outputs of the FREQUENCY DETECTORS 792 and 794. The O at the upper input of NOR gate 708 will coact with the O at the lower input of that NOR gate to apply a l to the lower input of NOR gate 706. Thereupon those NOR gates will act as an electronic latch which will maintain a continuous 0 on conductor 517, and hence at the second uppermost input of NOR gate 518, as long as switch 156 remains closed and keeps a 1 on conductor 778, and hence at the lower input of NAND gate 698.

Approximately 34 milliseconds after switch 162 closed, and hence approximately 334 milliseconds after switch 156 closed, BINARY COUNTER 254 will again apply a 1 to conductor 256. However, that 1 will not be significant at this time because conductors 258 and 260 are applying Os to the middle and lower inputs of NAND gate 272.

Approximately 60 milliseconds after switch 162 closed, and hence approximately 360 milliseconds after switch 156 closed, the vertical grid lines in the leading half of the upper portion of the portrait background will engage and start moving past the air gap of the magnetic head 208. That magnetic head will respond to those vertical grid lines to develop pulses, and amplifier 790 will amplify those pulses and apply them to conductor 791. The base of transistor 338 in the OVER- LEVEL SENSING sub-block 296 of FIG. 7 will receive those amplified pulses; but the amplitudes of those amplified pulses will not be great enough to cause that transistor to become conductive. Consequently, that OVERLEVEL SENSING sub-block will continue to supply a O to conductor 297. Those amplified pulses also will be applied to the base of transistor 682 in the BORDER sub-block 516 of FIG. 4; and that sub-block will respond to those amplified pulses to charge capacitor 712 and to forward bias diode 713, and thereby apply a 0 to the upper input of NOR gate 706. However, because that NOR gate and NOR gate 708 are acting as an electronic latch which maintains a continuous O on conductor 517, the amplified pulses which are applied to the BORDER sub-block 516 can not change the 0 on conductor 517, and hence can not cause a change in the Os at the lower inputs of NOR gates 800 and 802 in FIG. 3C.

The amplified pulses from amplifier 790 will be applied to the inputs of FREQUENCY DETECTORS 792 and 794; and the back-to-back diodes 858 and 860'in the former FREQUENCY DETECTOR and the counterpart back-to-back diodes, not shown, in the latter FREQUENCY DETECTOR will limit the values of the amplified pulses that are applied to terminal 3 of the phase locked loop 854 in the former FREQUENCY DETECTOR and to terminal 3 of the counterpart phase locked loop in the latter FREQUENCY DETEC- TOR. The phase locked loop 854 is set to respond to the signals which are developed by the magnetic heads 208 and 210 when the vertical grid lines of an authentic US. 1 dollar bill engage the air gaps of those magnetic heads while the lower runs of the belt 198 and its counterpart are moving an inserted bill at the rate of 10 inches per second; and the phase locked loop in FRE- QUENCY DETECTOR 794 is set to respond to the signals which are developed by the magnetic heads 208 and 210 when the vertical grid lines of an authentic US. 5 dollar bill engage the air gaps of those magnetic heads while the lower runs of the belt 198 and its counterpart are moving an inserted bill at the rate of 10 inches per second.

The oscillator of the phase locked loop 854 will tend to shift its center frequency to match the frequency of the amplified pulses which are applied to terminal 3 thereof; but the values of capacitors 866, 870 and 874 and of resistor 872 limit the shifting of that center frequency to plus or minus 5 percent of that center frequency. As a result, that phase locked loop establishes a desirably narrow pass band that will enable it to respond to amplified pulses which the magnetic heads 208 and 210 generate in response to an authentic US. 1 dollar bill but that will enable it to be unresponsive to amplified pulses which the magnetic heads 208 and 210 generate in response to a spurious 1 dollar bill. As the oscillator of the phase locked loop 854 locks on the frequency of the amplified pulses applied to the terminal 3, the 1 on conductor 795 will change to a 0; and hence NOR gate 800 will change the O at the output thereof to a l and will apply that l to the clock input of COUNTER 804. Inverter 819 will be responding to the 0 at output terminal 4 of that COUNTER to apply a I to the data input terminal of that COUNTER; and hence the l at the clock input of that COUNTER will cause that COUNTER to develop a l at output terminal 1 thereof. However, because that output terminal is not connected to anything, the development of the l at that output terminal is not significant. As long as the oscillator of the phase locked loop 856 remains locked on the frequency of the amplified pulses applied to the terminal 3, the 1 will continue to appear at 

1. A validator for documents which comprises a sensor that can respond to relative movement between itself and markings on a document to develop signals, means to provide relative movement between said sensor and said document to enable said sensor to respond to one group of markings on said document to develop a signal and to respond to another group of markings on said document to develop another signal, a sub-circuit which responds to the first said signal to develop an output signal at the end of a predetermined length of time after the termination of said first said signal if further markings are not sensed by said sensor within said predetermined length of time, a second subcircuit which responds to said other signal to develop a second output signal, means responsive to the development of the first said output signal to enable utilization of said second output signal if the first said output signal is developed by the first said sub-circuit before said second output signal is developed by said second sub-circuit.
 1. A validator for documents which comprises a sensor that can respond to relative movement between itself and markings on a document to develop signals, means to provide relative movement between said sensor and said document to enable said sensor to respond to one group of markings on said document to develop a signal and to respond to another group of markings on said document to develop another signal, a sub-circuit which responds to the first said signal to develop an output signal at the end of a predetermined length of time after the termination of said first said signal if further markings are not sensed by said sensor within said predetermined length of time, a second sub-circuit which responds to said other signal to develop a second output signal, means responsive to the development of the first said output signal to enable utilization of said second output signal if the first said output signal is developed by the first said sub-circuit before said second output signal is developed by said second sub-circuit.
 2. A validator as claimed in claim 1 wherein the first said sub-circuit includes a threshold detector, a timer and an output element, and wherein said output element can develop the first said output signal only when said threshold device does not receive signals from said sensor for a length of time controlled by said timer.
 3. A validator as claimed in claim 1 wherein the first said sub-circuit includes an electronic ''''latch'''' which responds to the development of the first said output signal to become latched and thereby enables said first said sub-circuit to remain in its latched state even though a further signal is supplied to said first said sub-circuit.
 4. A validator which comprises a sensor, means to provide relative movement between an authentic document and said sensor to enable said sensor to respond to markings on said authentic document to develop signals, a pattern detector which can develop a pattern signal as a given pattern, defined on said authentic document by some of said markings, is being sensed by said sensor, other of said markings on said document defining a border-like area which can cause said sensor to develop further signals, a sub-circuit that responds to said further signals which said sensor develops as said sensor senses said border-like area to develop a border signal, and means which responds to said border signal to enable utilization of said pattern signal, said means keeping said pattern signal from being utilized if said sub-circuit does not develop saId border signal.
 5. A validator which comprises a sensor, means providing relative movement between said sensor and a document, a detection circuit which can respond to the sensing of an authentic document of one type, a second detection circuit which can respond to the sensing of an authentic document of a second type, an inhibit circuit which can respond to a given signal to permit operation of said means but to inhibit the utilization of signals from said second detection circuit, and said inhibit circuit responding to a further signal to permit operation of said means but to inhibit the utilization of signals from the first said detection circuit.
 6. A validator as claimed in claim 5 wherein said inhibit circuit responds to simultaneous application of said given signal and of said further signal to prevent operation of said means and also to inhibit utilization of signals from both the first said and said second detection circuits.
 7. A validator which comprises a magnetic sensor, means to provide relative movement between said magnetic sensor and a document, a reversing circuit which responds to actuation thereof to cause said means to reverse and thereby return said document to the person who inserted it, a switch that responds to the insertion of a document to initiate actuation of said means, a threshold device which responds to signals from said magnetic sensor to determine whether the intensity of the magnetic material in the ink on said document is great enough to be comparable to that on an authentic document, and a second threshold device which will determine whether the amount of magnetic material in the ink on said document appreciably exceeds the amount on an authentic document, and said reversing circuit responding to a signal from said second threshold device or to the absence of a signal from the first said threshold device to become actuated and to reverse said means, and further means connecting the outputs of said threshold devices to said reversing circuit.
 8. A validator for documents which comprises a sensor that can sense markings on a document to develop signals, said sensor responding to one group of markings on said document to develop one signal and responding to another group of markings on said document to develop another signal, a subcircuit which responds to said one signal to develop an output signal but which delays the developing of said output signal for at least a predetermined minimum length of time after the termination of said one signal, a second sub-circuit which responds to said other signal to develop a utilizable output signal, and means which will enable utilization of said utilizable output signal only if the first said output signal is developed by the first said sub-circuit before said utilizable output signal is developed by said second sub-circuit, whereby said utilizable output signal will not be utilized if said sensor develops said other signal during the sensing of a document which does not have a group of markings thereon in position to be sensed by said sensor before said sensor senses said other group of markings.
 9. A validator which comprises a sensor, a second sensor, means to provide relative movement between said sensors and a document, the first said sensor being mounted to consecutively sense two spaced-apart areas on said document during said relative movement of said document and said sensors, said second sensor being mounted to engage two further spaced-apart areas on said document during said relative movement of said document and said sensors, at least one of said two spaced-apart areas on said document being physically in register with at least one of said two further spaced-apart areas on said document, and said sensors being spaced longitudinally relative to each other to enable said sensors to develop time-spaced sequential signals during the sensing of said one areas which are physically in register with each other.
 10. A validator which has a plurality of sensors that Are disposed to sense different areas on a document, said sensors being spaced longitudinally relative to each other to enable said sensors to coact with said different areas on said document to provide a plurality of signals which are spaced apart in time, means providing a given signal only if it receives said plurality of signals in time-spaced relation, one of said sensors sensing two spaced-apart areas on said document to develop two time-spaced signals, and said other of said sensors developing a signal during the time space between said two time-spaced signals which said one sensor develops.
 11. A validator which has a plurality of sensors that are disposed to sense different areas on a document, said sensors being spaced longitudinally relative to each other to enable said sensors to coact with said different areas on said document to provide a plurality of signals which are spaced apart in time, means providing a given signal only if it receives said plurality of signals in time-spaced relation, a sub-circuit that will develop an output signal in response to the signals which are developed when said sensors sense given areas on a document of one type, a second sub-circuit that will develop a second output signal in response to the signals which are developed when said sensors sense given areas on a document of a second type, and a third sub-circuit that will effect rejection of any document which causes the first said sub-circuit and said second sub-circuit to develop the first said and said second output signals simultaneously.
 12. A validator which has a plurality of sensors that are disposed to sense different areas on a document, said sensors being spaced longitudinally relative to each other to enable said sensors to coact with said different areas on said document to provide a plurality of signals which are spaced apart in time, means providing a given signal only if it receives said plurality of signals in time-spaced relation, a sub-circuit that will develop an output signal in response to the application thereto of signals having a predetermined frequency, a second sub-circuit that will develop a second output signal in response to the application thereto of signals having a different predetermined frequency, and a third sub-circuit that will effect rejection of any document which causes the first said sub-circuit and said second sub-circuit to develop the first said and said second output signals simultaneously.
 13. A validator which has a plurality of sensors that are disposed to sense different areas on a document, said sensors being spaced longitudinally relative to each other to enable said sensors to coact with said different areas on said document to provide a plurality of signals which are spaced apart in time, means providing a given signal only if it receives said plurality of signals in time-spaced relation said sensors being connected in series with one another, said series-connected sensors being connected to the input of an amplifier, said sensors successively applying consecutive but time-spaced signals to said amplifier, and said amplifier amplifying said consecutive time-spaced signals from said sensors.
 14. A validator which comprises a sensor, means to provide relative movement between said sensor and a document, an accept circuit, an inhibit circuit that is adapted to keep said accept circuit from developing an accept signal, and a signal sensing circuit which responds to signals developed by said sensor and which causes said inhibit circuit to inhibit said accept circuit if said signal-sensing circuit receives signals from said sensor while said sensor is sensing the area between predetermined spaced areas on said document.
 15. A validator which has a ''''line cording'''' circuit that comprises a selectively conductive device, an output sub-circuit that is connected to the output of said selectively conductive device, and an input sub-circuit that is connected to the input of said selectively conductive devicE, said input sub-circuit being connectable to a suitable voltage, said output sub-circuit being connectable to a lower voltage, said suitable voltage and said lower voltage responding to prolonged removal of power from said ''''line cording'''' circuit to decrease, and a voltage-dropping element in said input sub-circuit, said voltage-dropping element normally applying a voltage to the input of said selectively conductive device which will tend to hold said selectively conductive device in one state but said voltage-dropping element responding to reductions in said suitable voltage which can occur as power is removed from said ''''line cording'''' circuit to apply a different voltage to said input of said selectively conductive device which will cause said selectively conductive device to change to a different state, said voltage-dropping element applying said different voltage to said input of said selectively conductive device before any effective decrease could occur in said lower voltage as power is removed from said ''''line cording'''' circuit, and said selectively conductive device remaining in said different state if said lower voltage effectively decreases and continuing to remain in said different state until said lower voltage returns to its normal level.
 16. A validator as claimed in claim 15 wherein a source of voltage provides said suitable voltage and said lower voltage, and wherein said lower voltage is a regulated voltage.
 17. A validator as claimed in claim 15 wherein a source of voltage provides said suitable voltage, and wherein said lower voltage is a regulated voltage developed from said suitable voltage.
 18. A validator which comprises a first sensor, a second sensor, means to provide relative movement between a document and said sensors along a predetermined path, said sensors being displaced transversely of said path and also being displaced longitudinally relative to each other along said path, said first sensor responding to said relative movement between itself and said document to successively sense two longitudinally spaced areas on said document to provide two time-displaced signals, said second sensor responding to said relative movement between itself and said document to successively sense two further longitudinally spaced areas on said document to provide two further time-displaced signals, the longitudinal displacing of said sensors relative to each other enabling said first sensor to sense one of the first said longitudinally spaced areas on said document before said second sensor senses the first of said further longitudinally spaced areas on said document enabling said first sensor to sense the second of the first said longitudinally spaced areas on said document after said second sensor senses the first of said further longitudinally spaced areas on said document, and enabling said second sensor to sense the second of said further longitudinally spaced areas on said document after the first sensor senses the second of the first said longitudinally spaced areas on said document, and means to sense and respond to the signals developed by the first and second sensors as the first said longitudinally spaced areas on said document and said further longitudinally spaced areas on said document are sensed.
 19. A validator as claimed in claim 12 wherein said means includes a counter which receives said time-displaced signals and counts same.
 20. A validator as claimed in claim 18 wherein said time-displaced signals have frequencies, and wherein a phase locked loop operates as a frequency detector to determine whether said frequencies are within the pass band established by said phase locked loop.
 21. A validator which comprises a sensor, means that provides relative movement between said sensor and a document, said sensor responding to an authentic document to provide a predetermined signal, position-sensing means which develops a positional signal when a predetermined positional relationship occurs between said posiTion-sensing means and said document, a timer that includes a pulse source and a counter, said timer responding to said positional signal from said position-sensing means to cause said counter to start counting, and means that will develop a non-accept signal if said position-sensing means is still providing said positional signal but said sensor has not provided said predetermined signal prior to the time the count in said counter reaches a predetermined value.
 22. A validator which comprises a first position-sensing means, a second position-sensing means, means that provides relative movement between said first and said second position-sensing means and a document, said first position-sensing means developing a first positional signal when a predetermined positional relationship occurs between said first positional-sensing means and said document, said second position-sensing means developing a second positional signal when a predetermined positional relationship occurs between said second position-sensing means and said document, a timer that includes a pulse source and a counter, said timer responding to said first positional signal from said first position-sensing means to cause said counter to start counting, and means that will develop a non-accept signal if said first position-sensing means is still providing said first positional signal and if said second position-sensing means is not providing said second positional signal at the time the count in said counter reaches a predetermined value.
 23. A validator which comprises a position-sensing means, means that provides relative movement between said position-sensing means and a document, said position-sensing means providing a positional signal when a predetermined positional relationship occurs between said position-sensing means and said document, a timer that includes a pulse source and a counter, said timer responding to said positional signal from said position-sensing means to cause said counter to start counting, and means that will develop a not-accept signal if said position-sensing means is still providing said positional signal at the time the count in said counter reaches a predetermined value.
 24. A validator which comprises sensing means to sense a document and provide a predetermined number of separate and distinct signals, a counter which receives and counts said signals, said counter providing an output signal if the number of counts provided by said sensing means in response to the sensing of a given document equals, or differs by one from, said predetermined number of signals, said counter having a plurality of output terminals, said output terminals having a first state when said validator is at rest, said counter progressively changing said output terminals to a second state as said counter responds to said signals to count up to a pre-set number, said counter thereafter responding to further of said signals to progressively change said output terminals back to said first state, said output signal from said counter being developed as the second of two of said output terminals is changed to said second state, and said output signal from said counter being terminated as the first of said two of said output terminals is changed back to said first state.
 25. A validator which comprises sensing means to sense a document and provide a predetermined number of separate and distinct signals, a counter which receives and counts said signals, said counter providing an output signal if the number of counts provided by said sensing means in response to the sensing of a given document equals, or differs by one from, said predetermined number of signals, said counter having a plurality of output terminals, said output terminals having a first state when said validator is at rest, said counter progressively changing said output terminals to a second state as said counter responds to said signals to count up to a pre-set number, said counter thereafter responding to further of said signals To progressively change said output terminals back to said first state, said output signal from said counter being developed as the second of two of said output terminals is changed to said second state, said output signal from said counter being terminated as the first of said two of said output terminals is changed back to said first state, and switch means connected to said output terminals to permit changing of said pre-set number, and thereby permit changing of the output terminals which are said two output terminals.
 26. A validator for documents which comprises sensing means that can respond to relative movement between itself and markings on an authentic document to develop a signal having a predetermined frequency, means to provide relative movement between said sensing means and said document, and a phase locked loop which receives said signal and which responds to said signal to develop an output signal, said phase locked loop not responding to a signal from said sensor which has an appreciably different frequency.
 27. A validator as claimed in claim 26 wherein said document has a plurality of areas thereon that are sensed by said sensing means, wherein said sensing means responds to said plurality of areas to develop a plurality of signals having said predetermined frequency, wherein said phase locked loop responds to said plurality of signals having said predetermined frequency to develop a plurality of output signals, wherein a counter receives and counts said plurality of output signals, and wherein said counter will provide an output signal if the number of output signals from said phase locked loop equals, or differs by one from, from a pre-set number. 